1. Field of the Invention
The present invention relates to logic circuitry and, more particularly, to logic circuitry used to provide extremely rapid switching between output display frames in a computer system.
2. Discussion of the Prior Art
As computer systems such as work stations have grown more and more sophisticated, it has become clear that they might be conveniently utilized for providing the animation features that one associates with motion pictures and television. A computer which is capable of providing an animated output offers a distinct advantage over television and motion pictures because it, unlike the others, allows both the construction and revision of the images of animated displays. The ability of computers to provide three dimensional displays has hastened and heightened the desire for system which are capable of handling animated subjects.
A major problem in utilizing computers to provide animated output is that animation requires the display of frames which vary by small increments and succeed one another in rapid sequence. In order to display a single frame of graphical material on a cathode ray tube (CRT), it is necessary to store an indication of the information for each position (pixel) which is to appear on the output display. With large and detailed displays, the number of pixels on a cathode ray tube may average approximately one thousand in a horizontal direction and a like number in the vertical direction giving a total of approximately one million pixels about which information needs to be stored for each frame. In a preferred system which is capable of providing a number of different colors and hues on the cathode ray tube, twenty-four bits of digital information specifying the particular color output are stored for each pixel of the display. Consequently, approximately twenty-four million bits of information need to be stored for each frame to be presented at the output. This requires a substantial amount of time.
Moreover, not only does writing the approximately twenty-four million bits for each frame require a substantial amount of time, but the clearing of those bits in order to present the next frame requires an additional amount of time. Some of the delay between frames has been obviated by using double buffered systems in which two full screen bitmapped display memories are provided and switched alternately to the cathode ray tube output. Such a system reduces substantially the time between presentation of two frames of information but does not eliminate the need to clear each of the display memories so that it may be written with the color information for the frames which follow. Consequently, even such double buffered systems are too slow to provide optimum outputs for animation purposes.
An arrangement for decreasing the delay between individual frames is described in copending U.S. patent application Ser. No. 07/254,957, Apparatus for Rapidly Clearing the Output Display of a Computer System, Joy et al., filed Oct. 7, 1988, and assigned to the assignee of the present invention. This arrangement decreases the delay by essentially eliminating the time normally used for clearing the display memories in such a system. The system accomplishes this by providing full frame double-buffered bitmapped memories in which are stored indications that the information in the same position of an associated display memory part of in a particular frame. These memories are referred to as frame identification memories or buffers. Consequently each position representing a pixel in the twenty-four bit display memory has an associated, corresponding position in a four bit frame identification memory which identifies it by frame number.
When a frame which has been written into the display memory is to be read out, an output frame identification register is given the number of the frame to be read out; and that frame number is compared with the value of each position in the frame identification memory as the frame identification memory and the display memory are scanned for cathode ray tube refresh. Only those pixels which are in the selected frame are provided as output from the display memory to the cathode ray tube. At display memory positions at which the frame number in the output frame identification register and the number in the frame identification memory do not compare, a background color generator is activated to provide background color to the display. This allows frame-to-frame writing to the display memory to continue without clearing the display memory while clearing only a small portion of the frame identification memory. This dramatically reduces the intra-frame delay.
However, even this new arrangement offers an area for improvement because, even though the twenty-four bit display memories need not be cleared between frames, the pair of four bit frame identification memories must be cleared, either completely or in portions, before the next frame may be written. Moreover, although the use of frame identification memories allows the system to operate without clearing the larger display memories, it does add a significant amount of additional memory hardware to the computer system for use as frame buffer memory.
It is, therefore, an object of this invention to improve the speed at which images may be switched from frame to frame and presented at the output of a computer system.
It is another object of this invention to substantially reduce the delay associated with clearing frame identification memories between frames in a computer system.
It is another object of this invention to reduce the amount of memory hardware required to implement a frame identification memory in a computer system.
An additional object of this invention is to improve the speed at which computer systems operate.